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Cypress Semiconductor /psoc63 /FLASHC /FM_CTL /ANA_CTL1

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Interpret as ANA_CTL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MDAC0PDAC0NDAC0 (VPROT_OVERRIDE)VPROT_OVERRIDE 0 (R_GRANT_CTL)R_GRANT_CTL 0 (RST_SFT_HVPL)RST_SFT_HVPL

Description

Analog control 1

Fields

MDAC

Trimming of the output margin Voltage as a function of Vpos and Vneg.
PDAC

Trimming of positive pump output Voltage:
NDAC

Trimming of negative pump output Voltage:
VPROT_OVERRIDE

‘0’: vprot = BG.vprot. ‘1’: vprot = vcc
R_GRANT_CTL

r_grant control: ‘0’: r_grant normal functionality ‘1’: forces r_grant LO synchronized on clk_r
RST_SFT_HVPL

‘1’: Page Latches Soft Reset

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data